A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL (hardware description language) or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation.
An integrated circuit designer may use a set of EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The EDA application uses geometric shapes of different materials to create various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. During this process, the design components are “placed” (e.g., given specific coordinate locations in the circuit layout) and “routed” (e.g., wired or connected together according to the designer's circuit definitions).
Conventional EDA tool often performs various pattern matching operations for various purposes such as verification or optimization by invoking various EDA applications running on one or more computing nodes. Moreover, each of these EDA applications usually operates on an instance of the layout of the electronic circuit design to perform its own designated functions. For example, a layout editor may open an instance of the layout to perform its designated functions such as schematic entry, circuit simulation, custom layout, physical verification, extraction, etc. In the meantime, a place and route tool may open another instance of the layout to perform its placement and routing functions. Therefore, if there exists a problematic area within the layout, the user or designer often needs to invoke, for example, both the place and route tool and the layout editor to fix the problematic area in the layout. Such a process often involves one or more round-trips between the respective computing nodes on which the place and route tool and the layout editor reside or large amount of data transmission between the place and route tool and the layout editor.
Recent place and route tool development has envisioned so called DFM-aware (design for manufacturing) routers. In such an approach, the router is supplied with some rule-based or model-based DFM data to aid the router to route the design with potentially fewer DFM issues. Nonetheless, with the layout editor performing various verification and simulation functions, such an approach still requires transfer of vast amount of data between the placement and route tool and the layout editor.
Therefore, there exists a need for methods, systems, and articles of manufacture for smart pattern capturing and layout fixing.